[...]
> It isn't a special area of "scrathpad RAM". The 6x86MX allows you
> to lock down L1 cache lines. This means that the line will never
> be discard and hence you will never take a reload hit on the
> region of memory it is covering. Of course, you also have one
> less line of L1 cache available for general caching too...
locking L1 cachelines makes sense where the workload sweeps the L1 cache,
but the algorithm needs some (small) 'core cache area', to be fast. [but
which area is larger than can be stored in registers]
one such thing (mentioned before) are image processing algorithms, but the
same holds for RAID-5 checksumming. For RAID-5, we cannot store a full
cacheline worth of parity data in registers [and storing less kills most
L1 caches], so extra loads and stores are done. If a cacheline is locked,
we can store the RAID5 checksum there without worrying much about it
getting flushed to the L2 cache. [unless the L1 cache is _really_ smart
and finds out about linear loads and splits the cache into linear and
random cacheareas... dont know if there is any such processor]
on UltraSparc + VIS, several cachelines worth of parity data can be stored
in the FPU registers, which makes XOR-ing pretty darn fast.
on processors with MMX extensions, we can store two cachelines parity
data.
-- mingo