> I have produced a new small patch for Linux/6x86 users. The URL is
> http://www.tux.org/~balsa/linux/cyrix/Cyrix.patch-2
>
> It should patch cleanly against 2.0.x kernels and stock 2.1.6x kernels,
> although I have only tested it against 2.0.29.
>
> This patch will:
> 1) Correctly reset the 6x86(L) SLOP flag so that bogomips are correctly
> calculated on boot (on 6x86 CPUs, bogomips should _always_ be reported
> as the core clock rate +/- 1 MHz).
This is chipset dependant. As I reported previously, VXtwo and VXpro+
motherboards report totally different bogomips. The VXtwo will report the
bus clocking, sans multiplier, within 20MHz. The VXpro+ will report it to
20MHz within bus clocking, with multiplier. Both have the UMC8886/UMC8887
combo, which incorrectly reports in /proc/pci, as shown below.
[root@maezw /root]# cat /proc/pci
PCI devices found:
Bus 0, device 8, function 0:
VGA compatible controller: Texas Instruments Unknown device (rev 1).
Vendor id=104c. Device id=3d07.
Medium devsel. Fast back-to-back capable. IRQ 9. Master Capable.
Latency=32. Min Gnt=192.Max Lat=192.
Non-prefetchable 32 bit memory at 0xe1000000.
Non-prefetchable 32 bit memory at 0xe0000000.
Non-prefetchable 32 bit memory at 0xe0800000.
Bus 0, device 7, function 1:
IDE interface: VIA Technologies VT 82C586 Apollo VP-1 (rev 6).
Medium devsel. Fast back-to-back capable. Master Capable.
Latency=32.
I/O at 0x6000.
Bus 0, device 7, function 0:
ISA bridge: VIA Technologies VT 82C586 Apollo VP-1 (rev 37).
Medium devsel. Master Capable. No bursts.
Bus 0, device 0, function 0:
Host bridge: VIA Technologies VT 82C585VP Apollo VP-1 (rev 35).
Medium devsel. Fast back-to-back capable. Master Capable.
Latency=32.
FYI, the first device is a Diamond FireGL 1000 Pro.
And, as I said, this is a UMC board, not VIA. there is no VIA hardware on
it whatsoever. i'm not sure if this is caused by overlapping id's, or just
a typo in pci.h/pci.c. One of these days I will get around to fixing it.
:)
> 2) Correctly identify and report _all_ 6x86 CPU models and steppings in
> /proc/cpuinfo. This is new code _not_ based on Mike Jagdis' patch, so
> reports of (pos/neg) results are welcome.
Hrmm..
processor : 0
cpu family : 5
model : 6x86 2x Core/Bus Clock
vendor_id : CyrixInstead
stepping : 2 rev 2
that'd be nice, since i know this is a step2/rev7 chip. :)
-Phillip R. Jaenke [InterNIC Handle: PRJ5] (kernel@prj.pcimporters.com)
MIS Department, PC Importers, Inc. 800.319.9284, x4262
Head of Development, The Improvement Linux Project.
Penguin0: Cyrix Cx6x86 PR200L+, 64M, 1.6G, 1.2G, 4.3G, EE/Pro, 2.0.30
Penguin1: Intel P5-100, 32M, 4G, NE2k, 2.1.60-Improvement