> Then the code-flow is:
>
> (1) User executes bad instruction
> (2) CPU page-faults because IDT lower page is not present.
> (3) Kernel PF routine marks lower IDT page present.
> (4) Control returns to user (it's restartable).
> (5) User code traps to proper kernel handler.
> (6) Kernel handler marks IDT lower page not present.
*IF* you make two CPU's share one page table (not sure if this is done
or not), you have a problem (you map IDT there for CPU#0 and CPU#1
then dies to f00f ;-).
Pavel
-- I'm really pavel@atrey.karlin.mff.cuni.cz. Pavel Look at http://atrey.karlin.mff.cuni.cz/~pavel/ ;-).