Re: MTRR patch causes system lockups

David Wragg (
Mon, 19 Jan 1998 00:19:06 GMT

Emil Briggs writes:
> The P6SNE was purchased around a year ago -- the bios was flashed a
> month ago with the latest version posted at their web site. The other
> board is a brand new P6DNE so maybe this is a SuperMicro specific problem.
> Anyone else out there with a SuperMicro board who can confirm this?

Strange. My machine is over a year old, and the BIOS has never been

It seems that this kind of stuff is just typical of most PC component

> BTW -- when you say that you don't have the problem do you mean that
> passive release is already enabled on your board? Aaccording to the
> Intel document the problem occurs when "The USWC Write Posting during I/O
> bridge access enable (UWPIO) bit is set to 1. This bit is located in
> DBC (DBX Buffer Control) bit #5 in PMC at address offset 53h."

I mean that the Passive Release Enable bit is set by the BIOS. So the
patch I posted has no effect, since the bit is found to be set when
Linux boots - I even added a printk in there to make sure.

> This bit seems to be controlled by the write posting/combining settings
> in the bios -- If I shut these off the bit isn't set but the video
> performance is poor even with the mtrr patch which I guess makes
> sense because write combining is off even if the mtrr region is set
> up.

I've never actually confirmed that the UWPIO bit is set, but
write-combining certainly improves video performance so it must be. My
BIOS configurator doesn't seem to have options for it.

Dave Wragg