Yesterday I was wondering why I couldn't change
windows anymore in X... After a few hours I got this:
~ $date
Sat Apr 18 21:26:57 CEST 1998
~ $sleep 10 ; date
Sat Apr 18 21:26:57 CEST 1998
I've snooped arround a bit, script attached.
Resetting the clock from the rtc clock only worked a few
seconds. Rebooting solved the problem.
Groetjes, Peter
-- It's logic Jim, but not as we know it. http://hipe.uia.ac.be/~s950045 Look in keyservers for PGP key.--dDRMvlgZJXvWKvBx Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="stopping.clock"
Script started on Sat Apr 18 21:26:57 1998 ~ $uname -a Linux slartibartfast 2.0.33 #1 Sun Apr 12 12:11:30 CEST 1998 i586 unknown ~ $date Sat Apr 18 21:26:57 CEST 1998 ~ $sleep 10 ; date Sat Apr 18 21:26:57 CEST 1998 ~ $cd /proc/ /proc $cat cpuinfo processor : 0 cpu : 586 model : Pentium 75+ vendor_id : GenuineIntel stepping : 5 fdiv_bug : no hlt_bug : no f00f_bug : yes fpu : yes fpu_exception : yes cpuid : yes wp : yes flags : fpu vme de pse tsc msr mce cx8 bogomips : 35.84 /proc $cat interrupts 0: 5565727 timer 1: 92600 keyboard 2: 0 cascade 3: 23 + serial 4: 115636 + serial 5: 56 3c509 8: 2 + rtc 9: 59 SoundPort 11: 126432 + ncr53c8xx 13: 1 math error 14: 969 + ide0 15: 171353 + ide1 /proc $cat rtc rtc_time : 23:19:04 rtc_date : 1998-04-18 alarm : 19:11:37 DST_enable : no BCD : yes 24hr : yes square_wave : no alarm_IRQ : no update_IRQ : no periodic_IRQ : no periodic_freq : 1024 batt_status : okay /proc $cat modules serial 8 2 /proc $cat pci PCI devices found: Bus 0, device 12, function 0: SCSI storage controller: NCR 53c810 (rev 2). Medium devsel. IRQ 11. Master Capable. Latency=64. I/O at 0xe400. Non-prefetchable 32 bit memory at 0xfb7eb000. Bus 0, device 11, function 0: VGA compatible controller: Matrox Millennium (rev 1). Medium devsel. Fast back-to-back capable. IRQ 10. Non-prefetchable 32 bit memory at 0xfb7ec000. Prefetchable 32 bit memory at 0xfb800000. Bus 0, device 7, function 1: IDE interface: Intel 82371 Triton PIIX (rev 2). Medium devsel. Fast back-to-back capable. Master Capable. Latency=32. I/O at 0xe800. Bus 0, device 7, function 0: ISA bridge: Intel 82371 Triton PIIX (rev 2). Medium devsel. Fast back-to-back capable. Master Capable. No bursts. Bus 0, device 0, function 0: Host bridge: Intel 82437 (rev 2). Medium devsel. Master Capable. Latency=32. /proc $cat uptime 55707.58 23040.72 /proc $cat rtc rtc_time : 23:19:52 rtc_date : 1998-04-18 alarm : 19:11:37 DST_enable : no BCD : yes 24hr : yes square_wave : no alarm_IRQ : no update_IRQ : no periodic_IRQ : no periodic_freq : 1024 batt_status : okay /proc $date Sat Apr 18 21:26:57 CEST 1998 /proc $hwclock --show Sat Apr 18 23:20:36 1998 0.002088 seconds /proc $date Sat Apr 18 21:26:57 CEST 1998 /proc $date Sat Apr 18 21:26:57 CEST 1998 /proc $hwclock --hctosys --utc /proc $hwclock --show Sat Apr 18 23:21:01 1998 0.004499 seconds /proc $date Sun Apr 19 01:20:55 CEST 1998 /proc $date Sun Apr 19 01:20:56 CEST 1998 /proc $sleep 10 ; date Sun Apr 19 01:20:56 CEST 1998 /proc $exit exit Script done on Sun Apr 19 01:20:56 1998
--dDRMvlgZJXvWKvBx--
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