Re: faster strcpy()

Alan Cox (alan@lxorguk.ukuu.org.uk)
Mon, 27 Apr 1998 18:59:32 +0100 (BST)

> RvR> Strictly speaking, the NexGens and the K6 are RISC processors
> RvR> with an embedded x86 JIT compiler/interpreter.
>
> With that definition the good old 6510 in a C64 is a RISC processor.
> Remember microcode?

As is the Z80 ;)

> RISC is defined by the instruction set, not the implementation. A
> processor using the x86 instruction set can never be RISC, no matter
> the implementation

That goes for current MIPS, Alpha, Sparc too. The ARM is probably the closest
to the theoretical 'RISC' processor. On its gate count and power consumption you
can see the RISC concept really works

Alan

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