Re: patch to support peer PCI host bridges

Martin Mares (mj@atrey.karlin.mff.cuni.cz)
Thu, 30 Apr 1998 15:21:25 +0200


Hi,

> I'm new to Linux and this is my first post. I am running 2.1.97 on a Micron
> Powerdigm Xsu and found that the pci_scan_bus routine in drivers/pci/pci.c
> does not properly support peer host-PCI bridges (multiple bridges attached to
> the host bus). This is not a common configuration but the Powerdigm at least
> does implement peer host bridges. The peer host bridges must be configured
> with unique bus numbers in order to distinguish configuration space accesses
> (since the configuration registers overlay each other in memory in this
> situation). The patch follows (apologies if it is not in the correct format):

Does your patch really work? [Can you send me output of 'lspci -vvx' with
your patch applied?] There is one very strange thing: you reference the
PCI_PRIMARY_BUS register and several other bridge control registers, but they
are defined only for header type 1. Anyway, the byte at offset 0x0E in the
config space clearly says the host bridge has header type 0, so it should have
PCI_BASE_ADDRESS_2 in place of PCI_PRIMARY_BUS :-(

It seems Micron has done it in a very ugly way and we cannot use this method
for handling all peer host bridges (I'll look at the PCI specs as soon as I find
them in the huge pile of paper I've at my desk), so we will have to use it only
when find a Micron bridge.

> 00:19.0 Host bridge: Micron Samurai_1
> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
> SERR- FastB2B-
> Status: 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort-
> >SERR- <PERR-
> Latency: 32 set, cache line size 08
> 00: 42 10 10 30 07 00 a0 02 00 00 00 06 08 20 80 00
^^

Have a nice fortnight

-- 
Martin `MJ' Mares   <mj@ucw.cz>   http://atrey.karlin.mff.cuni.cz/~mj/
Faculty of Math and Physics, Charles University, Prague, Czech Rep., Earth
"Windows Error: 004 - Operator fell asleep while waiting."

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