> Note that the apic code really isn't SMP-specific at all, and is valid on
> its own. It does have a strong link to SMP mainly because the MP table
> contains the PCI routing information, but even that really isn't a SMP
> issue.
>
> So if somebody feels interested, it might be a good idea to split up the
> _real_ SMP code from the code that should be merely "CONFIG_APIC". That
> would give it more wider testing - and the newer APIC makes sense even on
> UP if for no other reason than the fact that is is much lower latency.
Interesting, indeed.
Just an idea:
Very low interrupt latency can make interrupt go ahead posted memory
write. I would suggest to check if all PCI device drivers do read an IO
register from the device in order to flush posted write just before
looking at the data.
A correct construct should look like the following:
read STATUS register
If interrupt condition
clear interrupt condition
-> READ a device IO register in order to force posted write flush.
look at the data written to memory by the PCI device.
Note that if the interrupt condition is cleared by an IO register read,
the additional READ is not needed, otherwise it should be IMHO.
Gerard.
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