Locking L1 cache lines in Cyrix 6x86MX CPUs

=?ISO-8859-1?Q?Andr=E9?= Derrick Balsa (andrebalsa@altern.org)
Tue, 19 May 1998 01:16:22 -0100

Hello Rik,

Rik van Riel wrote:
> > #I have a question. The 6x86MX allows one to lock L1 cache lines. Would
> > #it be interesting to group some kernel variables and keep them in the L1
> > #cache? Would that increase the kernel performance during context
> > #switches?
> >
> A good candidate would be the first lines of the
> task_struct and tss structs of the top 4 CPU using
> processes.
> Or maybe some very-often-used kernel structure.

The 6x86MX has 64Kb of dual ported L1 cache, running at full CPU speed,
without wait states or latencies. This cache is unified, meaning I could
lock lines for either short pieces of code and/or data.

So, my question really is: what are the most critical parts of the
kernel, in terms of execution speed, that would benefit from being kept
in the L1 cache permanently?

Has anybody done some profiling work in this area?

André Balsa

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