Re: Cyrix 6x86MX and Centaur C6 CPUs in 2.1.102

Stephen Williams (steve@icarus.icarus.com)
Mon, 18 May 1998 17:43:43 -0600

> On Mon, 18 May 1998, [ISO-8859-1] André Derrick Balsa wrote:
>
> #I have a question. The 6x86MX allows one to lock L1 cache lines. Would
> #it be interesting to group some kernel variables and keep them in the L1
> #cache? Would that increase the kernel performance during context
> #switches?

H.H.vanRiel@phys.uu.nl said:
> A good candidate would be the first lines of the task_struct and tss
> structs of the top 4 CPU using processes. Or maybe some
> very-often-used kernel structure.

Wouldn't such things possibly be cached anyhow?

How 'bout the interrupt stack (or least the beginning of it)?

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."






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