Re: Locking L1 cache lines in Cyrix 6x86MX CPUs

Phil's Kernel Account (
Mon, 18 May 1998 21:58:52 -0400 (EDT)

On Tue, 19 May 1998, André Derrick Balsa wrote:

#Hello Rik,

Hello everybody! *wave*

#The 6x86MX has 64Kb of dual ported L1 cache, running at full CPU speed,
#without wait states or latencies. This cache is unified, meaning I could
#lock lines for either short pieces of code and/or data.

That depends on the revision actually. I remember something about
quad-port cache. Also, keep in mind, earlier processors, such as the 5x86
do lack unified cache, but support cache locking, and others do NOT
support cache locking (IIRC), which would most likely result in an oops.
If someone can confirm or deny, it'd help. I trashed my 5x86 datasheets
ages ago. :(

#So, my question really is: what are the most critical parts of the
#kernel, in terms of execution speed, that would benefit from being kept
#in the L1 cache permanently?

There's almost certainly some static stuff that would increase performance
if locked into L1 cache. The problem is, figuring out exactly WHAT will
increase performance that remains static. :(


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