Rafael Reilova wrote:
>No difference at all! And during idle time the CPU is only consuming
>350mW, why do people insist on calling this a bug? Moreover on power up,
>suspend-on-halt is disabled, so there is no incompatability unless you
>fool around with the configuration registers. Let me repeat that, on
>power up the TSC is behaves *exactly* as the Intel Pentium TSC.
^^^^^^^^^
Maybe there are old 6x86MX chips with buggy TSC implementation. I'm now
quite confused between which 6x86 and 6x86MX have what bugs, and in which
steppings. Mine is identified as step.0.rev.3 and is fine.
Still for any known buggy versions the Cyrix specific init code can zero
the capability bit, right? Could someone confirm if the TSC is
implemented correctly on all Cyrix 6x86MX versions?
-- Rafael
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