Re: Locking L1 cache lines in Cyrix 6x86MX CPUs

Mike Jagdis (
Tue, 19 May 1998 10:24:43 +0100 (GMT/BST)

On Mon, 18 May 1998, Phil's Kernel Account wrote:

> That depends on the revision actually. I remember something about
> quad-port cache. Also, keep in mind, earlier processors, such as the 5x86
> do lack unified cache, but support cache locking, and others do NOT
> support cache locking (IIRC), which would most likely result in an oops.
> If someone can confirm or deny, it'd help. I trashed my 5x86 datasheets
> ages ago. :(

It's a while since I paid attention to the underlying architecture
but I seem to remember back when I was doing the non-Intel support
the 5x86/6x86 _didn't_ have cache line locking but it was promised
for the 6x86MX.

I did give some thought to possible uses though. Locking hot lines
doesn't seem useful. If lines are hot they are going to tend to
stay cached. If they aren't hot you probably have better things to
do with your cache. This is not so true with a direct mapped cache
because two, or more, hot locations can bounce a single cache line
backwards and forwards but, I think, all the Cyrix L1 caches are
associative (perhaps not the 5x86?) so it depends on the _exact_
method the chip's internals use to allocate cache lines.

The only time I can think of where you have significant and
_predictable_ trouble is when you want to read a region of memory
which is large with respect to the cooler part of the cache in
a linear and probably once only manner. Locking the cache lines
which are going to be used again might help the chip make good
decisions about which lines to use but how easy is it to figure
out which lines they are? Is it possible to take a fault or
interrupt while such an operation is in progress? If so you don't
want to have significant amounts of L1 cache unavailable - especially
if you could get rescheduled!

My own feeling is that this is not so useful as it might appear
at first glance. If you _really_ want to try something interesting
why not write a gcc back end that uses a locked L1 line as a nice
big register file and see if you can push the x86 architecture to
new heights?


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