> If you want to distinguish between
> - has no cycle counter
> - has a broken cycle counter
> - has a cycle counter that works as documented
> then that part I have no argument with. HOWEVER, if so, you'd better
> make it a new capability or something, because I don't want to have
> "real" kernel code having to care.
How about an extra bug field in the struct cpuinfo_x86?
If the TSC instructions are present, fill in the relevant bit in the
capability field, but if it's one of the broken chips, we set the bug flag too.
So the main kernel code can either just use them and be aware that they might
not conform strictly to the spec., or use an alternative, as the author sees
fit.
---- ---- ----
David Woodhouse, Robinson College, CB3 9AN, England. (+44) 0976 658355
Dave@imladris.demon.co.uk http://www.imladris.demon.co.uk
finger pgp@dwmw2.robinson.cam.ac.uk for PGP key.
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