Good or bad? [was Re: Locking L1 cache lines in Cyrix 6x86MX CPUs]

Pavel Machek (
Tue, 19 May 1998 16:21:44 +0200


> Hmmm. _Very_ interesting. I was thinking that perhaps the timer
> interrupt code could be kept in such a locked cache line, because on a
> busy machine it probably gets overwritten between the 10 ms periodic
> interrupts. But that's a hypothesis. Nobody seems to have quantitative
> data on this precise subject.

I think that this is *bad* idea: 10ms is not really often. And as
kernel usually eats <<1% of CPU time or less, stealing L1 cache lines
from userspace is probably going to be contraproductive.


The best software in life is free (not shareware)!		Pavel
GCM d? s-: !g p?:+ au- a--@ w+ v- C++@ UL+++ L++ N++ E++ W--- M- Y- R+

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