Re: Locking L1 cache lines in Cyrix 6x86MX CPUs

Rik van Riel (
Tue, 19 May 1998 15:01:17 +0200 (MET DST)

On Tue, 19 May 1998, Mike Jagdis wrote:

> My own feeling is that this is not so useful as it might appear
> at first glance. If you _really_ want to try something interesting
> why not write a gcc back end that uses a locked L1 line as a nice
> big register file and see if you can push the x86 architecture to
> new heights?

Hmm. That would probably be the best way of using it.
The other proposed usages don't seem to make any difference,
since often-used things tend to stay cached anyway and not
often used things don't really need to be cached...
(Except of course in low-latency things like interrupt
handling. It might be nice to trim some cycles off of
the interrupt handler. Maybe then we'll finally be faster
than QNX :)

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