Re: Locking L1 cache lines in Cyrix 6x86MX CPUs

Michael Meissner (
Tue, 19 May 1998 14:48:55 -0400

| I would start by reading the gcc source and studying the existing
| back ends for x86 and a register rich one like Alpha. Next year
| you might want to try changing a few things...

That won't help much, since the register allocation logic is all in mostly
machine independent code (there are various macros that control this, but the
logic is more in MI code). What kills on the x86, is not just the scarcity of
registers, but the fact that most of them have special uses. It is the special
use that really kills register allocation, due to some design decisions in the
register allocation.

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