Re: Locking L1 cache lines in Cyrix 6x86MX CPUs

Ben Pfaff (
19 May 1998 20:36:57 -0400

If we lock 1Kb of L1 cache lines, and use these adresses just as if they
were a uniform set of 256 32-bit registers, do you think this would
improve the performance of the code generated by gcc?

The compiler would just see them as R1-R256 and would have a homogeneous
instruction set relative to these R1-R256 (a very large subset of the
standard X86 instruction set).

These pseudo-register instructions would have the same CPU clock cycle
count as standard register instructions.

Unless I misunderstand, or the x86 instruction set has changed a great
deal since I last wrote in assembler, this isn't quite true, because
you can't use two memory operands in the same instruction; i.e., there
aren't any mov mem, mem or add mem, mem instructions.

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