Re: Cyrix 6x86MX and Centaur C6 CPUs in 2.1.102

Martin Mares (
Wed, 20 May 1998 10:15:48 +0200

> Also, we should take the intersection of all the capabilities in an
> SMP system.

Good idea, but then we would need to distinguish between "capabilities"
and "incapabilities" (we should assume buggy TSC if _any_ CPU has broken
TSC, but assume MMX instructions if _all_ CPU's have MMX instructions).
What about negating all the bug bits? (I.e., having a "working TSC" flag
instead of "buggy TSC" flag.)

Have a nice fortnight

Martin `MJ' Mares   <>
Faculty of Math and Physics, Charles University, Prague, Czech Rep., Earth
"A sine curve goes off to infinity or at least the end of the blackboard."

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