>There seems to be some terminology confusion here. There are two kinds
>of atomicicty... many CPUs provide an "atomic" test-and-set instruction
>which can not be interrupted (by interrupts, that is). These
>instructions usually are not atomic at the bus level, only at the CPU
>instruction level. Another bus master (a DMA device or another CPU) can
>access the same memory word inbetween the test and the set.
This is _not_ the needed atomicity for test_and_set_bit() I think...
>So another kind of atomicity is often provided which is guaranteed
>atomic even against other CPUs contending for the same word using the
I think this is the right atomicity for test_and_set_bit() (and i386
implement it in this way). Probably all ports are implementing
test_and_set_bit() in this way too just now so I think this is no more an
issue.
Andrea[s] Arcangeli
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