> I was wondering whether such draconian steep is necessary/justified in
> {Linux 2.1.105}:net/core/profile.c
>
> __initfunc(int net_profile_init(void)){
> [...]
> printk("Evaluating net profiler cost ...");
> [...]
> if (!(boot_cpu_data.x86_capability & 16)) {
> panic("Sorry, you CPU does not support tsc. I am dying...\n");
> return -1;
>
> As I think it could just disable profiling (at worst case) instead
> of using panic().
>
It should!
>
> The box would panic on me, when trying to boot 2.1.105. I'm not sure if
> this above is justifed. Was the Cyrix PR-200MMX the one with broken TSC?
> Beside that I don't think I did enabled Halt-On-Suspend explictly.
>
Just comment out the code that disables the tsc capability for Cyrix
chips. I think Linus stuffed it in bugs.h or in setup.c, just grep for
"Cyrix" in these two files.
The TSC in the Cyrix/IBM 6x86MX is _not_ broken, it works just like a
Pentium TSC when Suspend-on-Halt is not enabled explicitly.
This behaviour is independent of chip revision i.e. ALL Cyrix/IBM 6x86MX
chip revisions (including the new MII) will stop the TSC when entering a
Halt state IFF Suspend-on-Halt is enabled explicitly (it is normally
disabled).
Also, somebody posted an Oops on an AMD K5-90 machine a few days ago, in
routine do_fast_gettimeoffset(). This is because Linus forgot to copy
the relevant code that was originally in time.c on to setup.c; the said
code takes care of a similar problem with some AMD K5 revisions. A new
time.c will be available soon that solves this and other issues.
Cheers,
Andrew
BTW I wrote Cyrix about the 6x86MX TSC behaviour and they acknowledged
this difference between their CPUs and the standard Pentium behaviour.
Future MII revision will be changed so that the TSC keeps running even
when the CPU is Halted _and_ Suspend-on-Halt is enabled, at the cost of
a few extra mW dissipated.
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