on x86 it is not flushed across thread-thread switches ... and on a
PPro, parts of the TLB are tagged as 'global' (kernel pages
obviously), which keeps the TLB-lossage even across non-shared-VM
threads small. (zb->apache and apache->zb switches in this case).
I assumed that TSS switches were defined to reload csr3, which by
definition flushes the TLB of user entires.
Later,
David S. Miller
davem@dm.cobaltmicro.com
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