>On Tue, 23 Jun 1998, Marc Lehmann wrote:
>
>> no. could we solve this problem now? 4 byte alignment on pentiums is EVIL
>> EVIL EVIL. its worse than either zero or 16. Its a total waste of space.
>
>Can you prove this claim?
Intel's AP-500: Optimizations for Intel's 32-bit processors says:
"Prefetcher ... Alignment ... Pentium processor ... don't care"
(in the chapter 7 table)
Agner Fog's pentopt.txt says:
"Aligning code is not necessary on the PPlain and PMMX", where PPlain
means the standard Pentium CPU.
>I've seen results that show 4 byte alignment is *better* than 16 byte on a
>pentium because it reduces the cache footprint. Of course, this may be only with
Sure. And 0 byte alignment is even better (not for data bigger than 1 byte,
of course).
So is there even a single reason why the arch/i386/Makefile uses subject
line's flags for compiling a pentium kernel? Why not
-malign-loops=0 -malign-jumps=0 -malign-functions=0 ?
-- | Tuukka Toivonen <tuukkat@ee.oulu.fi> [PGP public key | Homepage: http://www.ee.oulu.fi/~tuukkat/ available] | Try also finger -l tuukkat@ee.oulu.fi | Studying information engineering at the University of Oulu +-----------------------------------------------------------
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