> > Hey, what's the problem with reprogramming the 8259s so that IRQ8 were
> > the highest priority interrupt?
> >
> > --
> Well, for one, its connected to the first chip through IRQ2, the
> 'cascade', so to make it the highest priority, the first chip would
> have to be even higher-priority which, by definition, is impossible.
OK, I'll explain what I meant in greater detail. We can set the IR2 line
of the master 8259 and the IR0 line of the slave one to have the highest
priorites. Then IRQ8 will be of the highest priority. If we set the PICs
to operate in the Special Fully Nested Mode then this setup will be even
more flexible.
> Then, the SMP machines don't use these controllers at all unless the APIC
> is broken.
But not all ia32 machines are SMP and these which are not have usually
the onchip APIC either absent or disabled. Unfortunately...
-- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
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