On 11 Jul 1998, H. Peter Anvin wrote:
>> > Then, the SMP machines don't use these controllers at all unless the APIC
>> > is broken.
>>
>> But not all ia32 machines are SMP and these which are not have usually
>> the onchip APIC either absent or disabled. Unfortunately...
>>
> Actually, the thing to use is the cycle counter if the CPU clock is
> anywhere near stable.
^^^^^^
Stable is the key word here. Just a remainder, APM and other power saving
tricks do make the CPU cycle counter "unstable" (by slowing down or even
stopping the CPU clock). Remember the TSC breakage with the Cyrix 686MX
and do_fast_gettimeoffset() when suspend on halt is enabled. For a
completely robust solution I think both methods are required, the TSC
*and* the CMOS or 8255 time interrupt (at least for non-APIC machines), to
compensate in case the CPU is subject to APM.
Of course, for embedded systems you have to deal with what is provided :-/
BTW, Scott Ananian was working on the TSC with APM thing some time ago,
but seems to have vanished. [Scott are you there?]
Cheers,
Rafael
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