Re: patch to trim page table cache

Alan Cox (alan@lxorguk.ukuu.org.uk)
Sat, 18 Jul 1998 20:15:17 +0100 (BST)

> Huh? On UP the cache size is the same, 25 pages at the low watermark,
> and this can make a difference to fragmentation. Furthermore, the
> preponderance of smaller memory machines are UP (does anyone have dual
> processors with only 16M?), so the unavailable memory is likely to be
> more important.

25 pages on an ARM3 box is 800K, on sane machines its much less signficant.
If this is an issue then turn it off on an 8Mb machine. The number of
8Mb SMP machines is small. Also at 8Mb the cache is relatively speaking
a sane size without our help

Alan

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