Re: S3 High Speed text font support in vgacon.c [patch 2.1.112]

Geert Uytterhoeven (Geert.Uytterhoeven@cs.kuleuven.ac.be)
Fri, 31 Jul 1998 17:38:50 +0200 (CEST)

On Fri, 31 Jul 1998, Gabriel Paubert wrote:
> > OK, this is a bit simplistic. I need two passes to prealloc the already
> > assigned stuff. I cannot reassign new adresses to already assigned stuff since
> > those adresses may be in the Open Firmware device tree properties, and thus
> > can't be changed.
>
> Well, you may have to find the free addresses. I was trying to write a PCI
> resource allocator and it's not that simple when you have bridges. I
> might have some working code next week. But why do you want to keep

Would be great... I don't forget you're the one who learned me that much about
PCI...

> the resources assigned by OF (I mean address space, not interrupts
> obviously) ? OF is not used after boot, after all.

It is. Some drivers use the address properties.

> Anyway current OF releases are still quite buggy and forget to allocate
> resources to all devices. This is plain wrong since it prevents you from
> using the components. I simply would not rely on OF resource allocation.

According to davem, on SPARC OF is rather reliable.

> > `lspci -v' gives for me (stripped irrelevant information):
> > | 00:03.0 VGA compatible controller: S3 Inc. Vision 968
> > | Flags: stepping, medium devsel, IRQ 28
> >
>
> It's not exactly like this: on my board lspci -vvx gives:
>
> 00:10.0 VGA compatible controller: S3 Inc. 86C764_1 [Trio 32/64 vers 1]
> Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
> ParErr- Stepping- SERR- FastB2B-
> Status: 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort- >SERR- <PERR-
> Interrupt: pin A routed to IRQ 15
> 00: 33 53 11 88 00 00 00 02 00 00 00 03 00 00 00 00
> 10: 00 00 00 3b 00 00 00 00 00 00 00 00 00 00 00 00
> ^^^^^^^^^^^
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 30: 00 00 ff ff 00 00 00 00 00 00 00 00 0f 01 00 00
>
> as you can see from the hex dump ;), the memory area has been allocated by
> the firmware at address 0x3b000000. lspci does not report it since memory
> accesses have not been enabled (Mem-).

00:03.0 VGA compatible controller: S3 Inc. Vision 968
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin A routed to IRQ 28
00: 33 53 f0 88 80 00 00 02 00 00 00 03 00 00 00 00
10: 00 00 00 fe 00 00 00 00 00 00 00 00 00 00 00 00
^^^^^^^^^^^
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 c4 00 00 00 00 00 00 00 00 0c 01 00 00

I.e. the `I need 32 MB' indicator (which is wrong: Vision968 needs 64 MB).
Thus nothing assigned.

> > | 00:05.0 VGA compatible controller: ATI Technologies Inc 215GT [Mach64 GT] (rev 9a)
> > | Flags: stepping, medium devsel, IRQ 30
> > | Memory at c2000000 (32-bit, non-prefetchable)
> > | Memory at fffff000 (32-bit, non-prefetchable)
> >
> > The first memory block of the RAGE II+ is assigned, the second isn't.
>
> Ok, it seems clear it is not assigned knowing the PPC architecture. But
> it could be perfectly valid on other architectures. So I believe that
> the S3 resources have not been assigned either.

It depends on the Open Firmware ROM on the ATI board. Newer boards have more
than 1 OF address property (Mine says c2000000 only), so I think they have all
apertures enabled.

Greetings,

Geert

--
Geert Uytterhoeven                     Geert.Uytterhoeven@cs.kuleuven.ac.be
Wavelets, Linux/{m68k~Amiga,PPC~CHRP}  http://www.cs.kuleuven.ac.be/~geert/
Department of Computer Science -- Katholieke Universiteit Leuven -- Belgium




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