You can thank 'Michel Aubry <giovanni@sudfr.com>' for the hard work
in determining the nature of the timings. He has run may tests, and
I trust the quality of his work without question. He is my inside source
the all VIA Chipset versions........
Please run timing tests with 'hdparam -tT /dev/hdx' and
report the results. I am interested in throughput gains or losses,
based on active configuring of VIA Chipset......
Michel, should this be done on a drive by drive basis?
I do this with a non-bootable UDMA chipset that is a WIP.
Note for all SPARC users of the IDE Chipset "ns87415",
there appears to be an introduction to chipset tuning
with a sledgehammer IMHO, with everything set to a default
tuning/timing value of DMA mode 2.
I propose that it may serve the driver better to let it do this
on a drive by drive basis. With the addition of blacklist of
drives that have been questioned of the DMA stability, I am
bothered by this blanket rule. If any drive that is not fully
capable of at least DMA mode 2, may give rise to fs-errors.
I make this assumption based on the following logic.
A drive is limited by the ablity of the controller and not
the other way around. If you limit the drive throughput via
software and not have it enforced by the controller, is
equivalent to a speed limit without police. You are bound
to be involved in a messy accident sometimes.
Cheers,
Andre
On Sat, 8 Aug 1998, Bernhard Rosenkraenzer wrote:
> On Fri, 7 Aug 1998, Andre M. Hedrick wrote:
>
> > VIA Chipsets should run two test.......since the addition of timing
> > tuning feature that must be set at compile time.
>
> Works well for me:
> ide0: VP_IDE Bus-Master DMA Timing Config Success
> ide1: BM-DMA at 0xfff8-0xffff, BIOS settings: hdc:pio, hdd:pio
> ide1: VP_IDE Bus-Master DMA Timing Config Success
> ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
>
> This is a VIA Apollo chipset:
> 00:07.1 IDE interface: VIA Technologies, Inc. VT82C586 IDE [Apollo] (rev 06)
>
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