1. I'm having real fun with the Z85230 synchronous stuff. I have now
got TX DMA working as well as tight loop polled transmit [*]
but RX DMA's off the chip are coming in with the first two bytes
missing. I've eliminated all the obvious suspects (next packet
arriving too quickly etc) and Im wondering if there are other 85230
people on the list with suggestions
2. When DMA is disabled reprogrammed and enabled will it generate any
extra DMA cycles as a result of the disable/enable. To use the
enhanced SCC RX DMA stuff I have to take an IRQ asynchronously
of the DMA flow, find out how many bytes the DMA controller has copied
beyond the desired packet, point the DMA at the right spot in the new
packet enable it and then memcpy the stuff that 'missed'
Before I write all the code to do this I was hoping folks would know
if thats a stunt the PC dma controllers can cope with.
[*] At 2Mbits with only one DMA channel available on some boards it does make
sense. Its under 1/100th of a second IRQ's off and even with IRQ's on the CPU
wouldnt do anything else but play tag with the PIC at that speed ;)
Alan
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