On Mon, 28 Sep 1998 12:01:33 -0500 (CDT), Chris Zwilling
<chris@cloudnet.com> said:
> I heard that the Xeon can not scale beyond four processors.
The Xeon has built-in logic to handle 4-way SMP. There's nothing to
stop you from implementing separate, off-CPU cache coherency logic for
larger numbers of CPUs. For example, Sequent have for some time made
a living from selling large SMP x86 systems, and I've used Sequent 386
and 486 arrays despite the fact that those CPUs have no built-in SMP
support at all.
--Stephen
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