Re: PCI_LATENCY_TIMER

Stephen Williams (steve@icarus.com)
Tue, 29 Sep 1998 14:47:50 -0700


The Latency Timer constrains the time (in PCI clocks) that a master may
hold the bus when the GNT# is removed. The latency timer is set by the
operating environment (BIOS or smart O/S) to control the maximum latency
of the PCI bus.

For example, if all the devices have a latency timer of 16, then it takes
no more then 16 clocks to free the bus for a new requesting master.

The MAX_LAT for a device tells the operating environment how much latency
this device can tolerate to operate efficiently. If I have a round-robin
scheduler with N potential masters, I might set the Latency timers for
all the devices to MAX_LAT/N where MAX_LAT is the smallest of all the reported
MAX_LAT values.

MIN_GNT tells the operating environment how long a burst I want, typically.
Latency Timer should be >= MIN_GNT, if that can be managed.

Others may dream up better ways of calculating Latency Timer values, but
any calculation of Latency timers should be a function of the MAX_LAT and
MIN_GNT values of the probed devices.

At least, that's the theory. Section 3.5 of the "PCI Local Bus Specification
Revision 2.1" goes into all kinds of gross detain on Latency issues.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

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