> > > The 2.1.x kernel trees have MTRR support, in 2.0.x you will have to do it
> > > directly. Basically on a P6 you can tell the CPU this memory area has
> > > these parameters - that includes "write gathering" - ie burst write.
> > Yes, I found MTRR support in kernel 2.1.x, but it only mentioned about
> > WC (Write Combined) attribute (as you mentioned above).
> > Is it possible to enable 'Read Cache' through MTRR ?
>
> I don't know.
Even if it is possible, what machanism will maintain coherency between the
cache and the remote memory which is seen through the system that has been
described in the initial mail.
The host brigde only snoops PCI write transactions and does not have
crystal balls to guess what happens in the PCI address range. For that,
it must access the corresponding locations.
The system that has been described is a simple PIO mode device.
The usual method to use efficiently the PCI bandwidth is to use Master
capable PCI devices, at least it is so for the moment.
In theory, an address range that is prefetchable can be read ahead using
bursts. We can imagine bridges capable to do that. In practice, host
bridges seem not to have been designed for such a feature.
Simple is elegant, but only when it works. ;-)
Regards,
Gerard.
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