Re: Dropped frames in video capture process

Rogier Wolff (R.E.Wolff@BitWizard.nl)
Fri, 6 Nov 1998 07:21:24 +0100 (MET)

Vassili Leonov wrote:
> >Subject: Re: Dropped frames in video capture process
> >Date: Fri, 6 Nov 1998 00:41:20 +0100 (MET)
> >
> >
> >Zoran designs pretty reasonable chips. They most likely have the
> >same setup as everybody else: if the overflow occurs, you see the
> >bit "set". If you read the status register, and write it back
> >with a "1" in the "fifo overrun" position, then that means you
>
> Well, I've read that place again, and can't see that. There is a
> place where manual says:

Page 27 of the datasheet.

13.6 Video Stride, Status and Frame Grab Register

This register contains parameters for display addressing (bytes 2-3),
status of VFIFO (byte 1) and frame grab control (byte 0). display.
Address Offset: 0x014 Bit
[....]
8 RC all VidOvf - Video FIFO Overflow flag. This bit is asserted by
the Video FIFO server when an overflow of the Video FIFO occurs. This
bit is cleared when the host tries to write '1' to it. In case of
concurrent accesses to this bit, it remains '1'.
'1' - a VFIFO overflow occurred.
'0' - no overflow (default value).

Case closed.

Roger. 

-- 
| Most people would die sooner than think....  |    R.E.Wolff@BitWizard.nl 
| in fact, most do.  -- Bertrand Russsell      |     phone: +31-15-2137555 
We write Linux device drivers for any device you may have! fax: ..-2138217


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