Let me add that I agree 100% with Gerard Roudier regarding a unified bus
address space, even with 100 PCI buses as Dave Miller suggests. We are
getting to the stage where we program devices to talk _directly_ to each
other -- and that will be very problematic if bus addresses vary between
buses.
(E.g., fast routing NIC -> NIC, video frame capture board ->
framebuffer).
Dave Miller wrote:
> So please propose a PCI addressing implementation that allows more
> than 1 PCI bus in the system and does not have the "problems" you see
> in sparc64 method :-) BTW, Alpha has something similar on multi-PCI
> bus machines and last I checked they were going to make it work the
> same way we did on sparc64.
Hey, I thought one of the *points* of 64 bit addressing was to unify all
the addresses in a machine!
The 32 bit address limitation of many PCI devices need not be a problem,
because when you've got 100 buses you need quite sophisticated bridging
-- so implement 64->32 address translation in the bridges if necessary
(keeping everything 64 bit wide on the CPU side and between bridges).
Though it's a bit late if the hardware's been built and can't support a
unified configuration.
-- Jamie
> MMIO is the simplest IO method that have been ever invented.
Er, disregarding caches, non-prefetchable vs. prefetchable, PPro MTRRs,
electrical timing constraints etc. ;-)
> With SUN's
> approach we may need address translations as:
>
> virt_to_bus_from_memory()
> phys_on_bus1_I_have_to_provide_bus2()
> bus1_address_as_seen_from_cpu_to_devices_on_bus2_address(....)
>
> Are you able propose a clean abstraction for that ?
Quite.
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