Re: Non-page-aligned PCI base address

Gerard Roudier (groudier@club-internet.fr)
Thu, 26 Nov 1998 22:21:12 +0100 (MET)


On Thu, 26 Nov 1998, Martin Mares wrote:

> Hello,
>
> > This sort of PCI base address assignement doesn't happen actualy often.
>
> Yes, especially because cards with memory regions smaller than
> page size are very rare.

Are you sure of your statement?

The preferred IO method for PCI is MMIO. Normal IO exists because of Intel
compatibility. PCI boards that donnot support MMIO are just shit because
they donnot take advantage of PCI posted writes.

> > This was the first case known to me and it happend on kind of exotic
> > board. But maybe it could be considered that future x86 mainboards are
> > going to have more than 4 PCI slots on multiple buses and therefore such
> > 'bug-feature' behaviour.
>
> This probably doesn't depend on number of PCI slots and buses at all.
>
> > The problem solution I'm thinking about could be some re-assignment of PCI
> > base addresses during setup of pci_dev, in the similar manner it is donne
> > with PCI interrupts:
> >
> > in pci.c:
> >
> > 1. check if the base address is page-aligned
> > 2. if not, see if is it possible to align it and on success
> > write new base addr into base config
> > 3. if the address is already used by other region, see if it is
> > possible to rearange other devices
> >
> > Does it make any sense ?

It does not because it is useless complexity.

> It would be possible, but certainly not before 2.3.

It would be stupid forever.

> Since this problem affects very small number of cards and therefore
> only a few drivers, it will be better to handle it in the drivers --
> instead of calling ioremap() directly, use
>
> new_base = (old_base & (PAGE_SIZE-1)) + ioremap(old_base & ~(PAGE_SIZE-1),...);

The formula is probably right and if only a few drivers are affected it is
because they use normal IO instead of the MMIO method recommended by PCI
specification.

Regards,
Gerard.

PS: Example: When the CPU performs a PCI memory write which is posted, it
only waits a few tens of nano-second. If an IO write is used instead, your
500 MHz CPU may wait several micro-seconds for the PCI BUS to be granted
to the host bridge and the transaction to complete. When a PCI to PCI
bridge is used it is even worse.

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