1024-way SMP?! (was Re: linux-kernel-digest V1 #2914)

Stephen C. Tweedie (sct@redhat.com)
Tue, 1 Dec 1998 15:26:08 GMT


On Mon, 30 Nov 1998 21:32:51 -0500, Paul Barton-Davis <pbd@op.net> said:

> Stephen C. Tweedie writes:
> ( on using 1024 cpus)

>> Binding that many CPUs together is hard! You tell me how you plan to do
>> it, and _then_ I'll tell you whether clustering is faster. :)

> I'd do it the same way that KSR did, except that I'd use off the shelf
> processors. Cornell, I think, had a 1024 node KSR-1 and maybe even a
> 1024 KSR-2. They never did get all the kinks out of their cache
> coherency protocol, but I think that between them and Alewife, it
> could probably be done.

Hahahaha. Have you *any* idea how bad the KSR interconnect scheme is
for SMP? I think the KSR cache line was something like 1024 bytes long,
as a compromise between bandwidth and latency. You just don't build
multicomputers that way, and you _certainly_ don't build SMP boxes that
way. Even today's 32-way NUMA boxes don't try to give a completely
uniform memory pool.

Don't get me wrong: KSRs were lovely boxes for prototyping on, because
they gave you the illusion of a big SMP system. However, their
performance was simply not up to it, precisely because they tried to
pretend that you didn't need to control communications explicitly at
that sort of scale.

> --p (still angry that UWashington could spend $1M on a KSR and then
> throw it away a year later)

Doesn't surprise me.


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