The CPU's on an X86 SMP box run a MESI cache. That means each cache line
has 4 states - those states dont include a 'shared-modified' state. So
when you have two people reading the same line and one writes it then the
other reads it you get
[M=modified E=exclusive S=shared I=invalid]
S S
E I
M I (data now written)
S S (data now readable)
The move from modified to shared especially is quite slow as it requires
the cache line is written to main memory and then read by the other CPU.
That will disturb any measurements because in CPU clock source counts thats
a long time. You probably need to measure this as well as measuring the
TSC difference some how to get a better view
Alan
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