Re: Still not perfect AMD detection

Dominik Kubla (dominik.kubla@uni-mainz.de)
Wed, 30 Dec 1998 14:35:01 +0100


On Wed, Dec 30, 1998 at 02:37:38AM +0000, Alan Cox wrote:
> >
> > Note the number 10 in flags line. Other information is correct.
> > 2.2.0-pre1+ac1+ide update, UP.
>
> Do you know what bit 10 is ?
>

I just checked the AMD K6-2 Processor Data Sheet. It states the following
bits in CR4 being used:

0 - VME (Virtual-8086 Mode Extensions)
1 - PVI (Protected Virtual Interrupts)
2 - TSD (Time Stamp Disable)
3 - DE (Debugging Extensions)
4 - PSE (Page Size Extensions)
5 - reserved
6 - MCE (Machine Check Enable)
7 - reserved
...
31 - reserved

Then there is the Extended Feature Enable Register (EFER, ECX=0xc0000080):

0 - SCE (System Call Extension)
1 - DPE (Data Prefetch Enable)
2/3 - EWBEC (EWBE Control)
4 - reserved
...
63 - reserved

And also the Processor State Observability Register (PSOR, ECX=0xc0000087):

0-2 - BF (Bus Frequency divisor) -> THERE ARE K6-2 with 66MHz FRONTSIDE BUS!
3 - reserved
4-7 - STEP (Processor Stepping)
8 - NOL2 (No L2 Functionality)
9 - reserved
...
63 - reserved

But no bit 10 in CR4...

Yours,
Dominik Kubla

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