Re: AMD K6 patch

Alexey Vyskubov (alexey@alv.stud.pu.ru)
Sun, 17 Jan 1999 11:48:05 +0300 (MSK)


Hello!

On 17-Jan-99 Mitchell Blank Jr wrote:
> Alexey Vyskubov wrote:
>> This is a bad patch for enabling "write allocation" on AMD K6 model 6,7
>> and
>> (maybe) K6-2 model 8. This stuff is in a wrong file, doesn't check CPU
>> type
>> and needs some hand tuning. But I wish to know people's opinion about
>> performance with this patch.
>
> It'd be nice if you included a discussion or a link describing exactly
> what write allocation does. I looked at www.amd.com and
> www.sandpile.org
> for about 10 minutes and didn't find too much enlightenment. <shrug>

Oops, the right name was "write allocate".

AMD 21326 application note "Implementation of write allocate in the
K86(tm) processors" says:

"Write allocate, if enabled, occurs when the processor has a pending memory
write cycle to a cacheable line and the line does not currently reside in
the L1 data cache. In this case, the processor performs a burst read cycle
to fetch the cache line addressed by the pending write cycle. The data
associated with the pending write cycle is merged with the
recently-allocated cache line and stored in the processor's L1 data cache.
The final MESI (Modified, Exclusive, Shared, Invalid) state of the cache
line depends on the state of the WB/WT# and PWT signals during the burst
read cycle and the subsequent cache write hit. During the write
allocation, a 32-byte burst read cycle is executed in place of a non-burst
write cycle. While the burst read cycle generally takes longer to execute
than the write cycle, performance gains are realized on subsequent write
cycle hits to the write-allocated cache line. Due to the nature of
software, memory accesses tend to occur within proximity of each other
(principle of locality). The likelihood of additional write hits to the
write-allocated cache line is high."

You can find this document on AMD web site.

--
With best wishes,
Alexey Vyskubov.
This is a message. Or something silly like that.

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