Most of the x86 L2 direct-mapped cache systems I've seen would
appear to be physically indexed and physically tagged, if I
understand your terminology correctly. The processor presents
physical addresses to the L2 cache, and the cache uses some of
the high-order physical address bits to tag cache lines.
I suppose there could have been virtually-indexed caches in the
days when the MMU was almost always external to the CPU, but I'm
not aware of any recent architectures where the processor's
external address bus uses virtual addresses.
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