another request for discussion:
With microseconds resolution there were many CPU cycles per
microsecond, but for nanoseconds there are multiple nanoseconds per
CPU cycle (at least this year).
Therefore variations when reading the cycle counter result in time
jitter at least, eventually maybe even in time running virtually
backwards occasionally.
The question is: "what assumptions can be made?" On the i386
architecture, will all cycle counters start at the same moment, and
will they be bound to the same oscillator? If not one has to
calibrate each CPU, and remember the cycle counter of each CPU during
timer interrupt. When getting the time one must find the cycle
counter of the own CPU and subtract that counter at the last
interrupt to get the difference. Other architectures maybe even worse.
Colin Plumb suggested to synchronize the cycle counters on i386
architecture, assuming they'll remain in sync. This would make the
time code much easier, but break things terrible, if the counters
drift apart.
Currently i386 issues are preferred, but you can give any suggestions
or hints you like.
Regards,
Ulrich Windl
P.S. I'm not subscribed here, so maybe CC:
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