Re: Questions about MMU design for PA-RISC
Anton Blanchard (anton@progsoc.uts.edu.au)
Thu, 11 Mar 1999 21:48:56 +1100
> I'm currently in the process of trying to get some PA-RISC MMU code
> into the kernel and due to some odd restrictions on the PA-RISC TLB
> handling, I'm looking for some advice on getting something working.
> Basically the PA-RISC has a software TLB (w/ possible hardware assist in
> some implementations, but I will be concentrating on software TLB
> handling for now) and one of the restrictions is that the TLB miss
> handler cannot fault on a TLB miss.
This sounds a bit like the sun4c mmu. Have a look at arch/sparc/mm/sun4c.c
where all necessary things are locked down to prevent a page fault inside
the kernel page fault handler.
Anton
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/