> Below is a patch against 2.2.5 that implements this.
Great!
> - O_SYNC disables caching by setting both the PCD and PWT bits.
> The extra PWT has no effect on Pentium and pre-Pentium systems. On
> the PPro and successors, both bits need to be set to disable
> caching whatever the MTRR type may be.
Ok, this is the important change. I will patch my 2.2.5 kernel (when
I get it compiled ;-) and try it out.
> So with this patch, O_SYNC can be used to map /dev/mem as uncached,
> without interactions with the MTRRs.
>
> It won't make any difference for non-Intel x86 processors (though
> it won't fix any similar problems they might have; I'd be grateful
> if anyone familiar with the memory type facilities on AMD and Cyrix
> processors could check this out).
We should do the same thing for non-Intel x86 processors, since I
believe they will work the same. We have both Cyrix 6x86 and K6/K6-2
systems here so I can test all of the above and see how they react to
the PCD and PWT bits. I hope they work in the same manner...
> (drivers/video/fbmem.c and drivers/video/sgivwfb.c use _PAGE_PCD
> and so probably need tweaking. But pgprot_noncached and
> noncached_address should be moved into arch-specific headers
> first.)
Right, the code in the kernel that implements the mmio_remapnocached
should be changed to set both the PCD and PWT bits to ensure the same
effect. Normally the MTRR's are never set up to cover PCI memory
regions for anything but graphics framebuffers (and also I have
discovered that if the 'Prefetchable' bit in the PCI base address
register is not set, the MTRR's don't appear to have any effect
either, but this could also be something that the chipset is doing to
disable caching directly).
Regards,
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