This is just setting up the virtual dma address mapping, right? It's
the same for PCI on the UltraSparc, and I believe gets hidden in the
implementation of ioremap in linux. I was going to add that to the
laundry list of PCI semantics - sometimes physical, sometimes virtual.
> Peter> For that matter, I don't think cache coherency affects
> Peter> readl/writel semantics [...]
>
> Oh yes cache coherency matters very much here if you want the drivers
> to work on the ARM boxes.
Consider the following sequence of driver events:
1. adapter DMAs into host memory
2. DMA completes
3. host reads DMA-ed data out of host memory
A non-cache-coherent bus means that you need to insert a magic step
between 2 and 3 to guarantee that the CPU reads the new data. (it
also affects the opposite process, where the CPU writes to host memory,
and then the adapter DMAs out of it)
Readl/writel deal entirely with memory spaces on the adapter card, not
in host memory, so their semantics *can't* be affected. In particular,
my example above can be constructed without the use of readl/writel
or any equivalent. (e.g. notice step 2 due to interrupt, do step 3 to
check if it's our interrupt. Major bug on non-cc PCI :-( )
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