Re: New resources - pls, explain :-(

Peter Desnoyers (pjd@fred001.dynip.com)
Tue, 17 Aug 1999 10:56:23 -0400 (EDT)

Jes Sorensen wrote:
>
> >>>>> "Peter" == Peter Desnoyers <pjd@fred001.dynip.com> writes:
>
> Peter> Consider the following sequence of driver events:
>
> Peter> 1. adapter DMAs into host memory 2. DMA completes 3. host reads
> Peter> DMA-ed data out of host memory
>
> Peter> A non-cache-coherent bus means that you need to insert a magic
> Peter> step between 2 and 3 to guarantee that the CPU reads the new
> Peter> data. (it also affects the opposite process, where the CPU
> Peter> writes to host memory, and then the adapter DMAs out of it)
>
> The correct place to put this is in front of 1, ie. before you even
> start the DMA.

As always, it depends. The UltraSparc can leave bits of the DMA'ed
data in its PCI bridges after the transfer completes, and you need to
explicitly flush the bus to make sure host memory and cache is in sync
with the device. Unless you've mapped the region in slow, synchronous
mode. Or so their documentation states - I've heard that real hardware
behavior isn't actually as bad as they tell Solaris driver writers.

Either way, it only affects DMA vs. host memory read/write semantics,
not readl/writel.

-- 
............................................................................
 Peter Desnoyers 
 162 Pleasant St.         (617) 661-1979          pjd@fred.cambridge.ma.us
 Cambridge, Mass. 02139   (978) 461-0402 (work)   pjd@giga-net.com 


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