>> Consider the following sequence of driver events:
>>
>> 1. adapter DMAs into host memory 2. DMA completes 3. host reads
>> DMA-ed data out of host memory
>>
>> A non-cache-coherent bus means that you need to insert a magic step
>> between 2 and 3 to guarantee that the CPU reads the new data. (it
>> also affects the opposite process, where the CPU writes to host
>> memory, and then the adapter DMAs out of it)
Philip> This is what the dma_cache_xxx functions defined in asm/io.h
Philip> are for.
Just notice that there is currently no cross-architecture definition
of these macros - all architectures name the differently and the ones
that are coherent don't have them at all.
Jes
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