A per bus coherency isn't sufficient. There are architectures which can
set cache coherency on a per device base. On SMPs this can avoid a
major amount of cross-CPU invalidates, therefore a good performance gain.
For architectures like this you want to leave the decission to the
driver writer.
Ralf
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/