Re: VIA chipset hangs???

Dan Hollis (goemon@sasami.anime.net)
Sun, 29 Aug 1999 21:53:24 -0700 (PDT)

On Sun, 29 Aug 1999, Andre Hedrick wrote:
> Greetings Martin,
> If we are discussing "CPU to PCI write buffer".
> 00:00.0 Class 0600: 1106:0597 (rev 04)
> 70: c1 88 ec 41 00 80 40 00 00 00 00 00 00 00 80 40 hangs
> 70: 41 88 ec 41 00 80 40 00 00 00 00 00 00 00 80 40
> ^--- here is the offending bit based upon imperical data.
> I will have to hunt through the "pdf's" again to verify that it has
> identical effects for all VIA chipset host-base.

>From the 597 (vp3) documentation:

Device 0 Offset 70 - PCI buffer control - RW
------------------------------------------------------------
Bit 7 - CPU to PCI Post-Write - 0 disable(default), 1 enable

I checked the documentation, and Device 0 Offset 70 bit 7 seems to be
exactly the same function for 595 (vp2/97), 598 (mvp3), and 691 (apollopro).

-Dan

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