Ok, let me clarify my point-of-view in this discussion:
I'd expect Linux to get the most out of the hardware. In this case,
transmissions achieving the full 115k2 on hardware that is capable of
that.
I'd -=like=- this to be achieved. If not, too bad. As long as it
works.
Well, let's see if we aren't not achieving that goal before we start
getting our knickers in a twist. I did my original performance tuning
and testing on an 40 MHz 386 with kermit transfers at 115kbps, and some
of the games in the driver (like not touching the ISR register since on
an 8 MHz ISA bus each I/O instruction really costs you) were done to get
performance as high as possible.
If we're having problems getting full 115k bps on hardware, especially
on today's hardware (i.e. Pentiums with IDE DMA), I'd be a little bit
surprised, quite frankly. But I'd really like to see some evidence that
that's the case before we add all sorts of complexity to the serial driver.
David is in a position where the gaps violate the spec, and he might
get caught in a situation where things actually don't work due to the
gaps.
If we have interrupt latency of > 4 character times at 9600 or 19200
bps, some other driver (or some hardware --- like the cheap sh*t IDE
contrllers that some boxes 2-3 years ago were inflicted with) has
serious bugs, and we should fix that driver first. That kind of
interrupt latency causes other problems besides ones for the serial
driver, and after a certain point it doesn't make sense putting huge
amounts of effort into making the serial driver more complicated than it
already is.
We optimize for the common case, after all, and it's becoming clear that
the Profibus case is not a friendly case; it looks like you will need to
disable the FIFO's in order to make it meet the spec anyway. And
without Profibus, if you have substandard hardware that requires turning
off the interrupts for huge amounts of time, I consider it acceptable
that you might not get full 115kbps transmission --- heck, sometimes on
such boxes you end up losing characters off the receive FIFO in any
case, so why bother optimizing the transmit side? Sometimes, it's just
not worth it.
- Ted
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