> Richard B. Johnson wrote:
> > Yes. Note that I write only one longword, then force new data onto
> > the bus by pushing/popping. They I read back. The cache is not going
> > to be loaded/reloaded from a single longword access.
>
> I know this is true on Pentiums, but is it true on P6 class machines? I
> would expect the `not [ebx]' to prefetch an entire cache line (possible
> from nonexistent memory), and the push/pop would not force anything onto
> the bus.
>
> On a P6, even a locked memory operation does not necessarily cause bus
> activity.
>
> Perhaps `wbinvd' is required. The Intel manual says: "Write back and
> flush internal caches; initiate write-back and flush of external
> caches".
>
I'll answer several questions including what you did not ask.
o The case of memory-mapped devices:
It's RAM. Until it is allocated for a driver it can be used
for RAM. It may be slow RAM, but it's RAM.
o Scattered writes/reads, i.e., a page appart should go
to the physical RAM. I have never seen it do differently.
If it didn't, you would not be able to use memory-mapped
I/O because the CPU would read its cache instead of physical
RAM.
Cheers,
Dick Johnson
Penguin : Linux version 2.3.13 on an i686 machine (400.59 BogoMips).
Warning : It's hard to remain at the trailing edge of technology.
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/